The present invention pertains to the field of digital memory circuits. More particularly, this invention relates to address structures and methods for selecting a data memory storage cell in a data storage array within a matrix of data storage arrays on a single substrate.
Many consumer devices are now constructed to generate and/or utilize digital data in increasingly large quantities. Portable digital cameras for still and/or moving pictures, for example, generate large amounts of digital data representing images. Each digital image may require up to several megabytes (MB) of data storage, and such storage must be available in the camera. To provide for this type of data storage application, the storage memory should be relatively low in cost for sufficient capacities of around 10 MB to hundreds of gigabytes (GB). The storage memory should also be low in power consumption, much less than one watt, and have relatively rugged physical characteristics to cope with the portable battery powered operating environment. For archival storage, data need only be written to the memory once. Preferably the memory should have a short access time (in the order of milliseconds) and moderate transfer rate (e.g. 20 Mb/s). Preferably, also, the storage memory should be able to be packaged in an industry standard interface module, such as PCMCIA or Compact Flash card.
One form of write-once compact information storage is shown in U.S. Pat. No. 6,055,180, granted to Gudesen et al. on Apr. 25, 2000, in which matrices of individually addressable cells are provided in layers between orthogonally arranged conductors. The cells may be comprised of cross-point diodes, OLEDs, bistable liquid crystal elements or other devices that change state with the introduction of heat and/or light.
Another application in portable devices for providing high density archival storage is described in co-pending U.S. patent application Ser. No. 09/875,356, filed Jun. 5, 2001 entitled xe2x80x9cNon-Volatile Memoryxe2x80x9d (Hurst, et al), the disclosure of which is hereby incorporated herein by reference. The memory system disclosed therein, referred to as portable inexpensive rugged memory (PIRM), aims to provide high capacity write-once memory at low cost for archival storage. This is realized in part by avoiding silicon substrates, minimizing process complexity and lowering areal density. The memory system includes a memory module formed of a laminated stack of integrated circuit layers constructed on plastic substrates. Each layer contains a cross-point diode memory array, and sensing of the data stored in the array is carried out from a separate integrated circuit remotely from the memory module.
FIGS. 1A and 1B show a typical PIRM memory structure on a substrate layer. The memory structure is comprised of a data storage array made up of a matrix of storage cell diodes at the intersections of row lines and column lines. Row and column decoder circuitry are connected to each of the row and column lines to address the selected storage cell diode. Row and column lines supply power to the data storage array.
In a further effort to compact data, multiple arrays are placed on a single substrate. FIG. 3 shows a two-by-two matrix of four memory arrays on a substrate. Each array has its own matrix of storage cells with corresponding row and column lines. Row and column address lines are connected through appropriate decoder circuitry to the rows and columns of each array.
As used herein, xe2x80x9ccoplanarxe2x80x9d means lying in the same plane. The term xe2x80x9ccoplanar conductor layerxe2x80x9d refers to a conductor layer in a data storage device like a cross-point memory cell in which all conductors in the layer are arranged in the same plane. The terms xe2x80x9ccoplanar memory array,xe2x80x9d xe2x80x9ccoplanar memory device,xe2x80x9d xe2x80x9ccoplanar memory matrixxe2x80x9d or xe2x80x9ccoplanar data storage cellxe2x80x9d refer to a memory array, device, matrix or data storage cell that has multiple planes or layers of like elements, such as a coplanar row conductor layer, a coplanar column conductor layer and a coplanar diode layer. In coplanar memory devices and arrays, all row conductor lines extend without cross-over in one plane or layer and all column conductors extend without cross-over in another plane or layer.
A coplanar memory array may contain two layers of conductors, an upper layer and a lower layer. Memory cell diodes may lie in a third plane sandwiched between the upper and lower layers. Arbitrarily, we can say that all row conductors and other conductors running horizontally in the figures are on the lower layer of the array and all column conductors and other conductors running vertically in the figures are on the upper layer of the array. On each layer, the conductors are not allowed to cross over one another, because such cross-overs would require additional difficult process steps, such as critically aligned vias. As used herein, the term xe2x80x9ccross-overxe2x80x9d refers to cross overs within an upper or lower layer, as described above.
The matrix of arrays shown in FIG. 3 shows the limits of conventional coplanar memory design wherein each array has column and row lines at one of the four corners of the two-by-two matrix of arrays. Using the memory array structure shown, in order to build a more complex matrix of arrays by adding more arrays in some fashion, cross-over lines would be needed, thereby defeating the coplanar lithography and requiring much more complexity in memory design.
Another problem with the memory matrices shown in FIGS. 1 and 3 is the undesirable dissipation of power. In the array design shown, all decoder resistors draw current during operation, thereby dissipating much more power than desired. Moreover, all data cell diodes that are not on a selected row or column are strongly reverse biased by the address line voltages. This reverse bias voltage causes undesirable leakage currents to flow in the unselected data diodes. In an array of up to ten million diodes, even a very small leakage current per cell can result in large power dissipation. In addition to this power loss problem, the leakage current may be large enough to interfere with or obscure the sense currents indicating the values of the selected data cells.
Accordingly, a different memory matrix design is needed to enable additional memory arrays to be placed on a single substrate in a coplanar design. Moreover, address structure is needed that minimizes or eliminates power dissipation from unselected cells, because of decoder resistor current and leakage current from reverse biased cells.
The present invention comprises novel structures and methods for disposing multiple memory arrays on a single substrate while maintaining a coplanar design with no cross-over lines. The present invention further comprises a coplanar multiple memory matrix having minimal power dissipation from undesirable current in unselected decoder resistors or from leakage current in unselected data cells.
In one embodiment, an electrically addressable data storage unit has a plurality of data storage arrays, each array having a matrix of data storage cells connected by row lines and column lines for recording, addressing and reading of data. The storage unit has a plurality of row address lines, each row address line being in electrical communication with the rows of predetermined multiple arrays of the plurality of data storage arrays. The data storage unit further has a plurality of column address lines, each column address line being in electrical communication with the columns of predetermined multiple arrays of the plurality of data storage arrays. A controller is connected to the plurality of row address lines and plurality of column address lines to selectively address a row of data storage cells in one of the multiple arrays and to selectively address a column of data storage cells in one of the multiple arrays, to thereby select a data storage cell in said one of the multiple arrays.
In another embodiment of the present invention, a method is provided for recording, addressing and reading of data in an electrically addressable data storage unit having a plurality of data storage arrays, each array having a matrix of data storage cells connected by row lines and column lines. A plurality of row and column address lines is provided for the plurality of arrays. Each row address line is in electrical communication with selected rows of multiple arrays to selectively address a row of data storage cells in one of the multiple arrays. Each column address line is in electrical communication with selected columns of multiple arrays to selectively address a column of data storage cells in one of the multiple arrays. A data storage cell in said one array is selectively addressed through a controller connected to the plurality of row address lines and plurality of column address lines.
Other aspects and advantages of the present invention will become apparent from the following detailed description, which in conjunction with the accompanying drawings illustrates by way of example the principles of the present invention.